منابع مشابه
CMOS switched current phase - locked loop
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In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملPhase Locked Loop Circuits
1. Definition. A PLL is a feedback system that includes a VCO, phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies mus...
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ژورنال
عنوان ژورنال: IEE Proceedings - Circuits, Devices and Systems
سال: 1997
ISSN: 1350-2409
DOI: 10.1049/ip-cds:19970907